search

sheldonucr / ucr-eecs168-lab

The lab schedules for EECS168 at UC Riverside
494 stars 32 forks source link

Lab 4 Fail to Compile Verilog Source Code #116

Closed MengEnLu closed 4 years ago

MengEnLu commented 4 years ago

image

clanktian commented 4 years ago

Same problem like this. T_T

jinweizhang001 commented 4 years ago

Please read the announcement sent shortly before T_T.

_Hi all,

The server software issue has been fixed, since there is only one week left before final week, we decided that you will be only working on partial of lab4 in next week lab session. The workload normally can be finished in one hour and is easier than lab3. In Lab4, the required parts are part 3 and part 4, part 2 is skipped, the rest parts (RTL synthesis for GCD) are determined as bonus points. The lab report due by next Sunday midnight.

TA_