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sheldonucr / ucr-eecs168-lab

The lab schedules for EECS168 at UC Riverside
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Cannot compile verilog files (part 2 of lab4) #119

Closed ryanmeoni closed 4 years ago

ryanmeoni commented 4 years ago

Attached are my attempts to compile the verilog code from both the lab4-rtl directory and the directory with the files: 168error

Is this the same issue as before?

MengEnLu commented 4 years ago

image yeah I have the same issue

yushuyuan commented 4 years ago

Yes, it's the same issue. Please SKIP part2 of the lab 4.