Problem with TLU+ setup

sheldonucr / ucr-eecs168-lab

The lab schedules for EECS168 at UC Riverside

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Open atorr048 opened 4 years ago

atorr048 commented 4 years ago

Screen Shot 2020-03-12 at 10 50 21 PM

I followed all the steps but I keep getting this error when importing the synthesized verilog file.

yushuyuan commented 4 years ago

Please check your fa_4bit.v file, if it still can not solve the problem, you may come tomorrow at the office hour.