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sheldonucr / ucr-eecs168-lab

The lab schedules for EECS168 at UC Riverside
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LVS Error for One Bit Adder: text_short #22

Open ldiaz011 opened 7 years ago

ldiaz011 commented 7 years ago

I have an error that I have no idea how to fix. It passes DRC but I get one error when I run LVS: I put the screen shot of my error and layout screen shot 2017-02-27 at 9 06 55 pm screen shot 2017-02-27 at 9 07 04 pm

Cwcook2 commented 7 years ago

I think you mixed up your p-implant and n-implant areas ( green and red boxes) unless you put your nmos on top and nmos on bottom. But it is hard to tell from the photo

Cwcook2 commented 7 years ago

The error you are getting is an extraction error also, not an LVS error. So maybe you did not name your nets correctly.

ldiaz011 commented 7 years ago

I switched the p and n implant and now I got this error: screen shot 2017-02-27 at 11 13 09 pm

Cwcook2 commented 7 years ago

unmatched nets mean that wires in your layout are not connected the same as your circuit. unmatched devices mean your have an extra transistor or are missing a transistor in your layout