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sheldonucr / ucr-eecs168-lab

The lab schedules for EECS168 at UC Riverside
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Lab 4 Verilog Issue #25

Open donei003 opened 7 years ago

donei003 commented 7 years ago

I'm having issues getting my code to pass the test bench. I thought we went through all my code and validated it in lab but I guess there are some errors still. Could you take a look at my code? I've attached the three files Lab.zip

nmlapre commented 7 years ago

Just wanted to add my name here - my code is very similar, and I'm having trouble passing the test cases as well.

ady002 commented 7 years ago

Same with me.

zergzerg commented 7 years ago

Hi, I checked your code and find some mistake in the control file. In the DONE state, you should set result_val to 1. BTW, make sure you use the correct mux_sel for A and B.

donei003 commented 7 years ago

Could you be more specific? I added the part the sets result_val to 1 but I am still failing the test bench

Cwcook2 commented 7 years ago

Dylan,

Make sure the signals driving your muxes are correct. For example, a mux may select in1 if sel=0 and in2 if sel=1. But you may be switching it around in your control unit. So make sure the mux sel is selecting right inputs.

-Chase

On Mar 14, 2017 4:57 PM, "donei003" notifications@github.com wrote:

Could you be more specific? I added the part the sets result_val to 1 but I am still failing the test bench

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donei003 commented 7 years ago

Yup, had some connections flipped (ex: I had B_mux_sel = A_reg when 1'b0, and initiliazed B_mux_sel to 1'b0 so it was getting A_reg instead of operands). All good now, thanks for the explaination!