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sheldonucr / ucr-eecs168-lab

The lab schedules for EECS168 at UC Riverside
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Lab #3 LVS Error (text_net:text_short) #71

Open adrianmoo2 opened 5 years ago

adrianmoo2 commented 5 years ago

I'm receiving an extraction error for my 1bit adder. I passed the DRC, but I'm not sure how I should go about debugging this error. Attached are pictures of my LVS output as well as my layout.

I marked the inputs & outputs (used M1Pin for the text labels) in the layout, as I know that it is hard to see.

image

layout

psythefirst commented 5 years ago

It means all the 7 networks are shorted. Please check the connection.

On Mon, Feb 25, 2019, 7:51 PM Adrian Tran notifications@github.com wrote:

I'm receiving an extraction error for my 1bit adder. I passed the DRC, but I'm not sure how I should go about debugging this error. Attached are pictures of my LVS output as well as my layout.

I marked the inputs & outputs (used M1Pin for the text labels) in the layout, as I know that it is hard to see.

[image: image] https://user-images.githubusercontent.com/14877762/53386202-1f709580-3936-11e9-9914-64385e26e393.png

[image: layout] https://user-images.githubusercontent.com/14877762/53386309-8726e080-3936-11e9-952b-96f2594e750b.png

— You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub https://github.com/sheldonucr/ucr-eecs168-lab/issues/71, or mute the thread https://github.com/notifications/unsubscribe-auth/AVD5A947O7mDAAhAQkit3VZKWJpNN98Oks5vRK82gaJpZM4bRS-n .

adrianmoo2 commented 5 years ago

I went to go grab food, and when I came back, I've been unable to run the LVS due to this strange error. Any idea on how to fix this?

image

psythefirst commented 5 years ago

Please refer to #52

adrianmoo2 commented 5 years ago

Hi, so I've changed my layout (I realized some of my inputs were not connected properly), and VDD is no longer shorted. However, the rest of them still are. I have trouble understanding how A is shorted in the layout. Do you think I could come to OH tomorrow to get some assistance?

Changed layout:

layou2

psythefirst commented 5 years ago

There seems to be a long M2 wire overlapped with an M1 wire shorting with other M2.

On Tue, Feb 26, 2019, 8:55 PM Adrian Tran notifications@github.com wrote:

Hi, so I've changed my layout (I realized some of my inputs were not connected properly), and VDD is no longer shorted. However, the rest of them still are. I have trouble understanding how A is shorted in the layout. Do you think I could come to OH tomorrow to get some assistance?

Changed layout:

[image: layou2] https://user-images.githubusercontent.com/14877762/53466907-a9892e80-3a08-11e9-9fca-cc6c8aa106a6.png

— You are receiving this because you commented. Reply to this email directly, view it on GitHub https://github.com/sheldonucr/ucr-eecs168-lab/issues/71#issuecomment-467724039, or mute the thread https://github.com/notifications/unsubscribe-auth/AVD5A8tERT4So5dONrBQw1lnC0x74xHxks5vRg-fgaJpZM4bRS-n .

adrianmoo2 commented 5 years ago

Hi,

I would like to thank you for your help earlier. I managed to debug almost all of my errors. However, I am having trouble understanding why my Cout in the layout is not matching with the schematic. Do you think you could help me with this issue?

couthelp

image

psythefirst commented 5 years ago

I think it is because you have Cout' and Cout all named Cout in the schematic

adrianmoo2 commented 5 years ago

I am a buffoon. Thank you.

adrianmoo2 commented 5 years ago

Debugged all of my errors. Thanks again!