shenpeifu / vtr-verilog-to-routing

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odinII : simulation #107

Open GoogleCodeExporter opened 9 years ago

GoogleCodeExporter commented 9 years ago
I try to simulate the output of odinII but i didn't find how to do it clearly.

Original issue reported on code.google.com by samehis...@gmail.com on 12 May 2015 at 10:06

GoogleCodeExporter commented 9 years ago
To simulate in Odin-II, you need to specify list of input signals along with 
their values directly in terminal or in a input vector file.

 SIMULATION: Always produces input_vectors, output_vectors,
             and ModelSim test.do file.
  Activate simulation with either: 
  -g <Number of random test vectors to generate>
     -L <Comma-separated list of primary inputs to hold 
         high at cycle 0, and low for all subsequent cycles.>
     -H <Comma-separated list of primary inputs to hold low at 
         cycle 0, and high for all subsequent cycles.>
     -3 Generate three valued logic. (Default is binary.)
  -t <input vector file>: Supply a predefined input vector file
  -U Default initial register value. Set to -U0, -U1 or -UX (unknown). Default: X
 Other Simulation Options: 
  -T <output vector file>: Supply an output vector file to check output
                            vectors against.
  -E Output after both edges of the clock.
     (Default is to output only after the falling edge.)
  -R Output after rising edge of the clock only.
     (Default is to output only after the falling edge.)
  -p <Comma-separated list of additional pins/nodes to monitor
      during simulation.>

Typical usage for simulation: ./odin_II.exe -a "$ARCH" -V "$benchmark" -t 
"$input_vectors" -T "$output_vectors"

$output_vectors: An output vector file to check output vectors against is 
optional.

Original comment by bbipinku...@gmail.com on 12 May 2015 at 11:17

GoogleCodeExporter commented 9 years ago
I wanted to know how to do simulation with Qt creator for blif file 

Original comment by samehis...@gmail.com on 12 May 2015 at 12:33