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shenpeifu / vtr-verilog-to-routing

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VTR and power #82

Open GoogleCodeExporter opened 9 years ago

GoogleCodeExporter commented 9 years ago 
Hello,
I was trying to run one of the benchmarks(sha) for power with visual studio. I 
ran ace separately and generated the activity file. But somehow the activity 
file is generating more signals that .blif I guess and VTR does not run. Have 
you see this before and could you please help me if I am going wrong somewhere??

What version of the product are you using? On what operating system?

VTR 7.0
Please provide any additional information below.

Original issue reported on code.google.com by deepaso...@email.arizona.edu on 28 Apr 2014 at 5:16

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GoogleCodeExporter commented 9 years ago 
Ace generates an activity file, and a new blif file.  Are you providing VPR 
with the original BLIF file (produced by ABC) or the new blif file (produced by 
ACE)?  Make sure it is the latter.

The reason for this is that ABC does not save internal node names.  When ACE is 
run it uses ABC to read the BLIF (which discards internal net names).  Then, 
activity estimation is performed and new net names are assigned to internet 
nets, and a new BLIF is produced with these names.  The new BLIF will be 
functionally identical to the OLD blif, but with different net names.

Original comment by jeffrey....@gmail.com on 28 Apr 2014 at 5:21

GoogleCodeExporter commented 9 years ago 
Thank You so Much for the info, I would try using the new blif file. We
would like to use the activity file generated by ace for including activity
factor of nodes ,for changes in router cost function. Could you give us
some pointers as to the data structures that I should be looking at  to
help me integrate that ?

Original comment by deepaso...@email.arizona.edu on 28 Apr 2014 at 5:32

GoogleCodeExporter commented 9 years ago 
s_net_power contains the probability/density values from the activity file for 
a net.

You may be interested in this work 
http://www.ece.ubc.ca/~eddieh/hung_fccm13.pdf.  They used the activity values 
to change the placement cost function, and measured the power difference on 
real FPGAs.

Original comment by jeffrey....@gmail.com on 28 Apr 2014 at 5:44