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shenpeifu / vtr-verilog-to-routing

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Preprocessing Verilog : ODIN Failed #92

Open GoogleCodeExporter opened 9 years ago

GoogleCodeExporter commented 9 years ago 
What steps will reproduce the problem?
1. ./odin_II.exe -V top_UART.v -a sample_arch.xml
2. Run in Icarus Verilog and the verilog file compiles and runs
3.

What is the expected output? What do you see instead?
 Synthesized blif file , ready for optimization using abc

What version of the product are you using? On what operating system?
Ubuntu, VTR Version 7.0 Full Release

Please provide any additional information below.

Original issue reported on code.google.com by david.dh...@gmail.com on 11 Jul 2014 at 7:02

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GoogleCodeExporter commented 9 years ago 
Trace/breakpoint trap (core dumped)

This is the latest error ODIN throws

Original comment by david.dh...@gmail.com on 11 Jul 2014 at 9:23

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