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Get information about the x86 and x86_64 processor

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Support Processor Extended State Enumeration Sub-leaf (EAX= 0DX, ECX = 1) #9

Closed gnzlbg closed 6 years ago

gnzlbg commented 6 years ago

From the Intel reference:

EAX

Bit 00: XSAVEOPT is available.
Bit 01: Supports XSAVEC and the compacted form of XRSTOR if set.
Bit 02: Supports XGETBV with ECX = 1 if set.
Bit 03: Supports XSAVES/XRSTORS and IA32_XSS if set.
Bits 31 - 04: Reserved.

EBX

Bits 31 - 00: The size in bytes of the XSAVE area containing all states enabled by XCRO | IA32_XSS.

ECX

Bits 31 - 00: Reports the supported bits of the lower 32 bits of the IA32_XSS MSR. IA32_XSS[n] can be set to 1 only if ECX[n] is 1.
Bits 07 - 00: Used for XCR0.
Bit 08: PT state.
Bit 09: Used for XCR0.
Bits 31 - 10: Reserved.

EDX

Bits 31 - 00: Reports the supported bits of the upper 32 bits of the IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1.
Bits 31 - 00: Reserved.