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shibatch / sleef

SIMD Library for Evaluating Elementary Functions, vectorized libm and DFT
https://sleef.org
Boost Software License 1.0
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RISC-V: exploit `-mrvv-vector-bits=zvl` when used #526

Open sh1boot opened 5 months ago

sh1boot commented 5 months ago

Here CONFIG=1 defaults to a run-time determination of the hardware vector length: https://github.com/shibatch/sleef/blob/cf532e214843c30023c269cf48aa7e84eaffb432/src/arch/helperrvv.h#L20

If the symbol __riscv_v_fixed_vlen is defined then the compiler is generating code which supports only that specified vector length (measured in bits), and we can lean into this by using the compile-time macro instead of the intrinsic call.

I have patches outstanding which edit this code, but they don't implement this suggestion. To make the change requires a bunch of extra CI permutations to test with and without -mrvv-vector-bits=zvl so it's not as trivial as it sounds.

CC: @luhenry

I don't expect a drastic performance gain, but it might help a little.

luhenry commented 5 months ago

-mrvv-vector-bits= should be the exception especially for the distribution of a binary/library as it would then be tied to whatever it was compiled for. Unless it's a functional requirement, or it's known that the binary is going to target a single class/model of hardware, then it's more pain than gain.