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shirriff / xc2064

Reverse engineering the XC2064 FPGA
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Where are you with this? #1

Open thetechknight opened 5 years ago

thetechknight commented 5 years ago

How far are you with this?

I have a board with 3 XC2018s in them that I need to figure out the function with. it has 2 serial bitstream eeproms that I will have to dump.

Just curious how far this script is along to be able to reverse the bitstream to figure out how these chips are programmed to work for my board.

Not trying to clone, just "run" the board with unknown dev docs because it was a proprietary system.

My board has two bitstream PROMs, and 3 daisy-chained arrays. https://drive.google.com/open?id=1h4WBZkEU2E792spkQESHL8ozRFtGqY3V

gbody commented 5 years ago

@mbates14 do you have a dump of the bitstream eproms. I should be able to help you turn them back into LCA readable file.

thetechknight commented 5 years ago

There are 3 FPGAs with 2 bitstream eeproms chained together that loads all 3 of them, so I have to come up with a way to read the eproms, I will probably make up some Arduino code to do it, unless you have a sketch or something I can use? They are those special Xilinx chips that would have complimented those XC FPGAs at the time of their release and use.

I will let you know when I have those dumped, I am basically trying to figure out how the logic works more than anything.

thetechknight commented 5 years ago

Hey, I was able to do a dump. Hopefully I have it dumped properly.

I have it arranged as a hexstring, LSB on the right, MSB on the left, just like windows calculator. Not sure how else you would want the file format?

Let me know if this works, Thanks.

https://drive.google.com/open?id=1TeoukzKUVMrKYc7q7WtjAwH39uNHmhWB

gbody commented 5 years ago

@mbates14 Here is the output of the file, it looks like the 2nd and 3rd device have the same configuration.

gbody commented 5 years ago

Doesn't look the file attached last time

thetechknight commented 5 years ago

I dont see any attachments or files?

BTW yes, Chips 2 and 3 are connected between DRAM and the 68K so chances are they serve as an arbiter between the 68K and the raster RAMDAC circuitry. Almost used in place of a dual-port RAM like VRAM.

I need to figure out what the 1st FGPA is doing most of all, its connected to an 8032/8051 CPU via the UART plus some extra external counters through a couple PALs.

gbody commented 5 years ago

XC2018.zip Also note the equations haven't been minimised.

thetechknight commented 5 years ago

Awesome! However, I have no idea what I am looking at. I see pins and nets, plus things in squiggly brackets, etc... All japanese to me.

Is there something to where I can see the logic with this? Somehow?

thetechknight commented 5 years ago

Also according to your readme, you mention 2 programs. I cant find either of them with a quick google search.

gbody commented 5 years ago

The software is Xact step and is DOS/Win3.1 compatible. I asked Xilinx for a copy to help migrate an old design

thetechknight commented 5 years ago

well I need a logic view of this stuff. I sent an email to Xilinx but I am not holding my breath considering everything that I see online says the software needs a license dongle.

Outside of that, Any ideas?

axelmuhr commented 5 years ago

Hey gbody, I'm trying to do something similar than mbates14 and can't persuade the python script to run. Attached is a 1736 PROM dump for an XC2064... could you please be so kind and do your magic again? Thanks a ton!

NC.zip