sibradzic / amdgpu-clocks

Simple script to control power states of amdgpu driven GPUs
GNU General Public License v2.0
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Can't apply anything with amdgpu-clocks #59

Closed Pacarius closed 6 months ago

Pacarius commented 6 months ago

When i ran amdgpu-clocks with the following file:

OD_VDDGFX_OFFSET: -100mV

I get this::

Detecting the state values at /sys/class/drm/card1/device/pp_od_clk_voltage: SCLK state 0: 500Mhz SCLK state 1: 2590Mhz MCLK state 0: 97Mhz MCLK state 1: 1219MHz VDD GFX Offset: 0mV Maximum clocks & voltages: SCLK clock 5000Mhz MCLK clock 1500Mhz Unexpected value in /sys/class/drm/card1/device/pp_od_clk_voltage:12

and my /sys/class/drm/card1/device/pp_od_clk_voltage looks like this:

cat /sys/class/drm/card1/device/pp_od_clk_voltage OD_SCLK: 0: 500Mhz 1: 2590Mhz OD_MCLK: 0: 97Mhz 1: 1219MHz OD_VDDGFX_OFFSET: 0mV OD_RANGE: SCLK: 500Mhz 5000Mhz MCLK: 97Mhz 1500Mhz VDDGFX_OFFSET: -450mv 0mv

My gpu is a 7800xt hellhound, i am running arch 6.8.1, and i think i am running mesa 24.0.4-2.

sibradzic commented 6 months ago

Hi @Pacarius, thanks for reporting.

The VDDGFX_OFFSET: -450mv 0mv in your pp_od_clk_voltage looks super weird and does not look like it belongs there, at least not in the vanilla kernel. For comparison, here is my pp_od_clk_voltage (Arch, vanilla kernel 6.8.4-arch1-1, RX 6600 XT):

cat /sys/class/drm/card1/device/pp_od_clk_voltage
OD_SCLK:
0: 700Mhz
1: 2524Mhz
OD_MCLK:
0: 97Mhz
1: 1000MHz
OD_VDDGFX_OFFSET:
-70mV
OD_RANGE:
SCLK:     500Mhz       3150Mhz
MCLK:     674Mhz       1200Mhz

You said you are running arch 6.8.1, but your pp_od_clk_voltage does not look like a normal vanilla amdgpu driver. Are you perchance running custom or zen kernel or custom driver?

Or maybe the 7800XT HellHound has PP_OD_FEATURE_GFX_VF_CURVE_BIT enabled?!? Can you please share your /sys/class/drm/card1/device/pp_table? It is binary file, so either encode it in bas64 & dump as a comment or share via some file sharing service...

Pacarius commented 6 months ago

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I don't know if this is correct, i just found the first base64 convertor online and dropped my dumped pp_table in, so if it doesn't work please let me know. also, I'm at least 99% sure I'm running vanilla arch with vanilla drivers, at least as of rn.

sibradzic commented 6 months ago

The dump looks good, thanks. I'll be looking into it later today...

sibradzic commented 6 months ago

OK, according to your pp_table dump

echo "obase=2;$(upp -p /tmp/Powercolor.RX7800XT.Pacarius.pp_table get smc_pptable/SkuTable/OverDriveLimitsBasicMax/FeatureCtrlMask | tail -n1)" | bc
11111001101

and this, your card does have PP_OD_FEATURE_GFX_VF_CURVE_BIT set (the rightmost bit above), which means the output in your pp_od_clk_voltage may be valid after all. This means you'll need an updated script.

Can you try this patch:

--- a/amdgpu-clocks
+++ b/amdgpu-clocks
@@ -86,6 +86,10 @@ function parse_states() {
         MAX_MCLK=${LINE##* }
         MAX_MCLK=${MAX_MCLK%*M[Hh]z}
         ;;
+      "VDDGFX_OFFSET: "*)
+        echo "    VDDGFX offset range: ${LINE#*: }"
+        OFFSET_RANGE=${LINE#*: }
+        ;;
       "VDDC: "*)
         echo "    VDDC voltage ${LINE##* }"
         MAX_VDDC=${LINE##* }

?

Pacarius commented 6 months ago

looks good! after running the patched script the vddgfx offset properly applies! ----------------------------------Detecting the state values at /sys/class/drm/card1/device/pp_od_clk_voltage: SCLK state 0: 500Mhz SCLK state 1: 2575Mhz MCLK state 0: 97Mhz MCLK state 1: 1219MHz VDD GFX Offset: 0mV Maximum clocks & voltages: SCLK clock 5000Mhz MCLK clock 1500Mhz VDDGFX offset range: -450mv 0mv Curent power cap: 228W Verifying user state values at /etc/default/amdgpu-custom-state.card1: VDD GFX Offset: -100mV Committing custom states to /sys/class/drm/card1/device/pp_od_clk_voltage: Done [....@.... amdgpu-clocks]$ cat /sys/class/drm/card1/device/pp_od_clk_voltage OD_SCLK: 0: 500Mhz 1: 2575Mhz OD_MCLK: 0: 97Mhz 1: 1219MHz OD_VDDGFX_OFFSET: -100mV OD_RANGE: SCLK: 500Mhz 5000Mhz MCLK: 97Mhz 1500Mhz VDDGFX_OFFSET: -450mv 0mv

Thx <3