Implement SFence Instructions

[llee454]

The Sfence instruction selectively flushes the TLB cache. Implement the fine-grained behavior documented in the Priv-mode spec.

For the common case that the translation data structures have only been modified for a single address mapping (i.e., one page or superpage), rs1 can specify a virtual address within that mapping to effect a translation fence for that mapping only. Furthermore, for the common case that the translation data structures have only been modified for a single address-space identifier, rs2 can specify the address space. The behavior of SFENCE.VMA depends on rs1 and rs2 as follows: • If rs1=x0 and rs2=x0, the fence orders all reads and writes made to any level of the page tables, for all address spaces.66 Volume II: RISC-V Privileged Architectures V20190125-Public-Review-draft • If rs1=x0 and rs26 = x0, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2. Accesses to global mappings (see Section 4.3.1) are not ordered. • If rs16 = x0 and rs2=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for all address spaces. • If rs16 = x0 and rs26 = x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for the address space identified by integer register rs2. Accesses to global mappings are not ordered.

[llee454]

"The FENCE.I instruction was designed to support a wide variety of implementations. A sim- ple implementation can flush the local instruction cache and the instruction pipeline when the FENCE.I is executed." RISCV-spec, 31