Add AXI properties

[drom]

AXI4

• number of outstanding transactions
• number of outstanding reads
• maximum reordered reads
• Per channel: does Ready combinationally dependent on Valid?

[drom]

Example: https://github.com/sifive/block-pio-sifive/blob/master/docs/pio.json5#L153

[mwachs5]

Looking at duh-scala, we are currently using something called "canInterleave" which I believe is not captured in the duh-bus for AXI4:

https://github.com/sifive/duh-scala/blob/master/lib/axi4-tl.js#L37

[mwachs5]

For reference, here is all properties in Tile Link needed to parameterize:

an AXIMaster

case class AXI4MasterParameters(
  name:      String,
  id:        IdRange       = IdRange(0, 1),
  aligned:   Boolean       = false,
  maxFlight: Option[Int]   = None, // None = infinite, else is a per-ID cap
  nodePath:  Seq[BaseNode] = Seq())
...
case class AXI4MasterPortParameters(
  masters:    Seq[AXI4MasterParameters],
  echoFields:    Seq[BundleFieldBase] = Nil,
  requestFields: Seq[BundleFieldBase] = Nil,
  responseKeys:  Seq[BundleKeyBase]   = Nil)

an AXISlave

case class AXI4SlaveParameters(
  address:       Seq[AddressSet],
  resources:     Seq[Resource] = Nil,
  regionType:    RegionType.T  = RegionType.GET_EFFECTS,
  executable:    Boolean       = false, // processor can execute from this memory
  nodePath:      Seq[BaseNode] = Seq(),
  supportsWrite: TransferSizes = TransferSizes.none,
  supportsRead:  TransferSizes = TransferSizes.none,
  interleavedId: Option[Int]   = None,
  device: Option[Device] = None) // The device will not interleave responses (R+B)
...
case class AXI4SlavePortParameters(
  slaves:     Seq[AXI4SlaveParameters],
  beatBytes:  Int,
  minLatency: Int = 1,
  responseFields: Seq[BundleFieldBase] = Nil,
  requestKeys:    Seq[BundleKeyBase]   = Nil)

I think many of these can be derived from the widths of signals, but not all:

[drom]

Looking at duh-scala, we are currently using something called "canInterleave" which I believe is not captured in the duh-bus for AXI4:

https://github.com/sifive/duh-scala/blob/master/lib/axi4-tl.js#L37

And it is mapped to interleaveId property. Do you know the meaning?

AXI4SlavePortParameters(
      slaves = Seq(
        AXI4SlaveParameters(
          ...
          interleavedId = ${canInterleave ? 'Some(0)' : 'None'},
          ...

[drom]

Here are some potential candidates for properties:

{
  writeInterleavingDepth: {
    type: 'integer', minimum: 0,
    title: 'Write Interleaving Depth',
    description: 'Master can not issue more write transactions than slave can accept.'
  },
  readReorderingDepth: {
    type: 'integer', minimum: 0,
    title: 'Maximum Reordered Reads',
    description: 'Slave can not reorder more read transactions than master can accept.'
  },
  writeReorderingDepth: {
    type: 'integer', minimum: 0,
    title: 'Maximum Reordered BResps',
    description: 'Slave can not reorder more write transactions than master can accept' 
  },
  outstandingReads: {
    type: 'integer', minimum: 0,
    title: 'Maximum number of outstanding read transactions',
  },
  outstandingWrites: {
    type: 'integer', minimum: 0,
    title: 'Maximum number of outstanding write transactions'
  },
  outstandingTransactions: {
    type: 'integer', minimum: 0,
    title: 'Maximum number of outstanding transactions'
  }
}

[drom]

merged