I describe interrupt component to the duh document, but it's not implemented after chisel wrapper generation using 'duh-export-scala' command. to be more precise, interrupt wiring is not executed.
this is what I described interrupt component in the json5
......
"intr": {
name: "irq",
interfaceMode: "master",
busType: {vendor: "sifive.com", version: "0.1.0", library: "free", name: "interrupts"},
abstractionTypes: [
{
viewRef: "RTLview",
portMaps: [
'hightemp_int',
]
}
],
},
......
this is a part of the generated chisel wrapper (*-base.scala)
......
class LmifBaseImp extends LazyRawModuleImp(this) {
...
// interface wiring
val irq0 = irqNode.out(0)._1
...
// wiring for irq of type interrupts
// ["hightemp_int"]
...
}
......
I think below line is should be include in the generated chisel wrapper.
......
// wiring for irq of type interrupts
// ["hightemp_int"]
irq0(0) := blackbox.io.hightemp_int
......
I describe interrupt component to the duh document, but it's not implemented after chisel wrapper generation using 'duh-export-scala' command. to be more precise, interrupt wiring is not executed.
this is what I described interrupt component in the json5 ...... "intr": { name: "irq", interfaceMode: "master", busType: {vendor: "sifive.com", version: "0.1.0", library: "free", name: "interrupts"}, abstractionTypes: [ { viewRef: "RTLview", portMaps: [ 'hightemp_int', ] } ], }, ......
this is a part of the generated chisel wrapper (*-base.scala) ...... class LmifBaseImp extends LazyRawModuleImp(this) { ... // interface wiring val irq0 = irqNode.out(0)._1 ... // wiring for irq of type interrupts // ["hightemp_int"] ... } ......
I think below line is should be include in the generated chisel wrapper. ...... // wiring for irq of type interrupts // ["hightemp_int"] irq0(0) := blackbox.io.hightemp_int ......