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sifive / duh-verilog

🇻Verilog import / export package
Apache License 2.0
2 stars 1 forks source link

attach formal checkers for known bus interfaces. #2

Open drom opened 4 years ago

drom commented 4 years ago

https://github.com/ZipCPU/wb2axip/blob/master/bench/formal/faxil_slave.v