Open iDoka opened 4 years ago
Would be nice to define version of verilog to output. I not mean version 1995, but as I can in README by default using SV syntax. Unfortunately, in 2020y some people or even Co still using pure verilog in ASIC design flow.
Good point. Will add.
Would be nice to define version of verilog to output. I not mean version 1995, but as I can in README by default using SV syntax. Unfortunately, in 2020y some people or even Co still using pure verilog in ASIC design flow.