While creating a duh document (json5) using duh init command following are the fields which need to be filled in
$ duh init slaveapbi2ssynopsys.json5
? Document file name slaveapbi2ssynopsys.json5
? Block name SynopsysApbI2sSlave
? version 0.1.0
? Please write a short description about the block
? Block type component
? Source type Verilog
In the above options can there be a new field for blackbox name since in the verilog top level modules that i have access to, have an _ in their name. Now in the current duh it uses the Block name in all the class names in the generated scala source files due to which we can't uses Block name with an _ the workaround for which is to manually edit *-base.scala to change blackbox name to actual one which contains _
While creating a duh document (json5) using
duh initcommand following are the fields which need to be filled in $ duh init slaveapbi2ssynopsys.json5 ? Document file name slaveapbi2ssynopsys.json5 ? Block name SynopsysApbI2sSlave ? version 0.1.0 ? Please write a short description about the block ? Block type component ? Source type Verilog In the above options can there be a new field for blackbox name since in the verilog top level modules that i have access to, have an_in their name. Now in the current duh it uses the Block name in all the class names in the generated scala source files due to which we can't uses Block name with an_the workaround for which is to manually edit *-base.scala to change blackbox name to actual one which contains_