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duh
👾 Design ∪ Hardware
https://observablehq.com/@drom/duh-intro
Apache License 2.0
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clean all unused references in the definition section
#27
drom
opened
5 years ago
1
duh-export-verilog-bbx CLI
#26
drom
closed
5 years ago
0
use duh schema from duh-schema
#24
drom
closed
5 years ago
2
Verilog to json5
#23
shiviarorasifive
closed
5 years ago
3
How is mycom-busprop.json supposed to be interpreted/used?
#22
ghost
closed
5 years ago
1
provide better error message when verilog pinlist import fails
#21
drom
closed
5 years ago
0
added duhportinf as a dependency
#19
abishara
closed
5 years ago
0
infer-channels
#18
drom
closed
5 years ago
1
Verilog integration
#16
drom
opened
5 years ago
0
SystemRDL integration
#15
drom
opened
5 years ago
0
get command
#14
drom
closed
5 years ago
0
generate Scala wrapper for Scala / Chisel designed blocks
#13
drom
closed
5 years ago
1
display Test coverage report
#12
drom
closed
4 years ago
0
display Verilator code coverage report
#11
drom
opened
5 years ago
0
support logicalTieOff in portMap
#9
drom
opened
5 years ago
0
user parameter schema
#8
drom
opened
5 years ago
0
add clock / reset definition
#7
drom
opened
5 years ago
0
generate editable Datasheet from component schema and config
#6
drom
opened
5 years ago
0
component CSR section
#5
drom
closed
5 years ago
0
Verilog black box generator
#4
drom
closed
5 years ago
0
add scaffolding generator
#2
drom
closed
5 years ago
1
add component spec schema
#1
drom
closed
5 years ago
0
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