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SiFive Intel FPGA Direction Request #131

Open jtarango opened 4 years ago

jtarango commented 4 years ago

Hi Team,

I have been working to integrate the SiFive generated processor to a Intel FPGA synthesis, place, and route. Based on the implementation from Xilinx, it does not seem to be an appropriate fit for the tool chain to be partitioned in the current ordering. The code is a demo of what it looks like to integrate into the tcl and a single make file. The current approach I believe it would be best to use a single makefile that takes a file tree input.

Please let me know your thoughts and advice for the best path to integrate. The code in its current state is not ready to push and awaiting a decision from SiFive.

erikdanie commented 4 years ago

Hi Joe,

First off, thanks for the work you've done here! Are you asking if it is okay to make an entirely new synthesis flow for Altera boards? If so, the answer is yes. The tcl scripts are totally vendor specific, so it doesn't matter at all that one looks like the other. Does the code here work as is? What boards have you tested it with? I am willing to merge this stuff as long as we can label it as experimental

jtarango commented 4 years ago

Hi Erik Danie,

Thank you for the response and please excuse the delay, I have had some task forces I had to context switch within Intel. The promote request to review the potential automation build paths for the open source repo. The path that I duplicated for the Intel-Altera flow from the Xilinx flow is a frankenstein from the simple one make file we can have for the Altera-Intel tools. Would it be possible to set up a live meeting to discuss the changes and give advice on which approach to go towards for Intel integration? I believe the technical advice would help to fully automate the Intel build process and future integration to the Intel One API.

On Wed, May 20, 2020 at 7:06 PM Erik Danie notifications@github.com wrote:

Hi Joe,

First off, thanks for the work you've done here! Are you asking if it is okay to make an entirely new synthesis flow for Altera boards? If so, the answer is yes. The tcl scripts are totally vendor specific, so it doesn't matter at all that one looks like the other. Does the code here work as is? What boards have you tested it with? I am willing to merge this stuff as long as we can label it as experimental

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-- Joseph Tarango