Problem interfacing JTAG to RTL project built from SiFive folder

[kfrey101]

The overall goal is to recreate the bit file without the additional peripherals that is provided in the tar file when a new core is configured. I created a top level wrapper to interface to the RISC-V verilog core on the Arty A7 board.

I/O signals for the module are

 input   CLK100MHZ,

 // Debug header interface 

output     JD1,  // goes to TDO
output     JD2,  // goes to nTRST
 input      JD3,  // goes to TCK

 input      JD7,  // goes to TDI
 input      JD8   // goes to TMS

//output JD9 // goes to nRST

Settings inside the module are as follows

// ---------------------------------------------------

assign system_clock = CLK32MHZ; //assign system_reset = !ck_rst; // active high signal

assign system_psd_test_clock_enable = 0;

assign system_debug_clock = CLK32MHZ;

assign system_external_source_for_core_0_clock = CLK32MHZ;

assign JD3 = system_debug_systemjtag_jtag_TCK; assign JD8 = system_debug_systemjtag_jtag_TMS; assign JD7 = system_debug_systemjtag_jtag_TDI; assign JD1 = system_debug_systemjtag_jtag_TDO_data;
assign JD2 = system_debug_ndreset;

assign system_debug_systemjtag_jtag_TDO_driven = 1; // enable the TDO going into the Debug module

assign system_debug_systemjtag_mfr_id = 11'b0; assign system_debug_systemjtag_part_number = 16'b0; assign system_debug_systemjtag_version = 4'b0;

assign system_debug_dmi_block = 1'b0; assign system_debug_dmactiveAck = system_debug_dmactive;

assign system_debug_extTrigger_out_ack = 2'b0; assign system_debug_extTrigger_in_req = 2'b00;

// Set this to zero on power up. assign system_reset_vector_0 = 32'b0;

assign system_meip_0 = 1'b0;

assign system_nmi_0_rnmi = 1'b0; assign system_nmi_0_rnmi_interrupt_vector = 32'b0; assign system_nmi_0_rnmi_exception_vector = 32'b0;

assign system_rtc_toggle = 1'b0;

When I launch the Freedom Studio and try to run the debugger I get the messages below.

Open On-Chip Debugger 0.11.0+dev (SiFive OpenOCD 0.11.0-2022.08.0) Licensed under GNU GPL v2 For bug reports: https://github.com/sifive/freedom-tools/issues debug_level: 0

jtag probe Using JTAG Error: [riscv.cpu] DMI operation didn't complete in 2 seconds. The target is either really slow or broken. You could increase the timeout with riscv set_command_timeout_sec. Error: [riscv.cpu] DMI operation didn't complete in 2 seconds. The target is either really slow or broken. You could increase the timeout with riscv set_command_timeout_sec. Error: [riscv.cpu] DMI operation didn't complete in 2 seconds. The target is either really slow or broken. You could increase the timeout with riscv set_command_timeout_sec. Error: [riscv.cpu] DMI operation didn't complete in 2 seconds. The target is either really slow or broken. You could increase the timeout with riscv set_command_timeout_sec. Error: Target not examined yet