what does unimp a0 a1 mean?

[XiaPZ]

I am reading fsbl/main.c, and I see some code at line 404-424:

int slave_main(int id, unsigned long dtb)
{
  // Wait for the DTB location to become known
  while (!dtb_target) {}

  //wait on barrier, disable sideband then trap to payload at PAYLOAD_DEST
  write_csr(mtvec,PAYLOAD_DEST);

  register int a0 asm("a0") = id;
#ifdef SKIP_DTB_DDR_RANGE
  register unsigned long a1 asm("a1") = dtb;
#else
  register unsigned long a1 asm("a1") = dtb_target;
#endif
  // These next two guys must get inlined and not spill a0+a1 or it is broken!
  Barrier_Wait(&barrier, NUM_CORES);
  ccache_enable_ways(CCACHE_CTRL_ADDR,14);
  asm volatile ("unimp" : : "r"(a0), "r"(a1));

  return 0;
}

What does asm volatile ("unimp" : : "r"(a0), "r"(a1)); mean? It sinces there is no unimp in riscv specs.

[jim-wilson]

On Fri, Nov 23, 2018 at 12:02 AM D.pz notifications@github.com wrote:

What does asm volatile ("unimp" : : "r"(a0), "r"(a1)); mean? It sinces there is no unimp in riscv specs.

unimp is an unimplemented instruction, guaranteed to cause an illegal instruction trap. It is encoded as all ones.

Jim

[XiaPZ]

@jim-wilson that is clear, thanks a lot for your reply

[palmer-dabbelt]

@decentsheep are you seeing a bug around here? The code you listed is horrible but usually works.

[XiaPZ]

@palmer-dabbelt no bug yet, I am just reading the source code

[MarcKarasek]

Is there a reason mtvec is used to write the PAYLOAD_DEST and then a trap (unimp) is used to jump to this address for each hart? Instead of just jumping to it like from ZSBL -> FSBL??