Closed yintianyu closed 5 years ago
See my branch here where I am attempting to do the same thing. Specifically the diff in /src/main/scala/everywhere/e300artydevkit/System.scala
@erikdanie I have just switch to your branch besides every submodule. After modifying several import lines(as well as other lines maybe), I could finally generate verilog.
However, when generating mcs, it failed as followed:
ERROR: [Synth 8-439] module 'AnalogToUInt' not found [/home/yinty/code/freedom/freedom-bump/builds/vc707-u500devkit/sifive.freedom.unleashed.DevKitU500FPGADesign_WithDevKit50MHz.v:283823]
Parameter WIDTH bound to: 32'sb00000000000000000000000000000001
ERROR: [Synth 8-285] failed synthesizing module 'VC707BaseShell' [/home/yinty/code/freedom/freedom-bump/builds/vc707-u500devkit/sifive.freedom.unleashed.DevKitU500FPGADesign_WithDevKit50MHz.v:283675
I find AnalogToUInt
( along with UIntToAnalog
) in fpga-shells/src/main/scala/shell/Util.scala
where it is a BlackBox
module.
So where can I find these modules, are they Xilinx IPs? How can I use them when synthesizing?
You need to edit the makefile to have VSRCS variable point to that path
Actually I don't know which path or file to be added to VSRCS
since I cannot find a verilog module named AnalogToUInt
in any vsrc folder. I even suspect that it isn't a verilog module.
Ah I see, these were never open-sourced, though they are really simple, and there's no reason they shouldn't be. The reason I hadn't done it yet is that IOBUF is preferred to AnalogToUInt and UIntToAnalog, but I hadnt gotten around to replacing them yet. (https://github.com/sifive/fpga-shells/blob/master/src/main/scala/ip/xilinx/Unisim.scala#L235)
Here is the code if you care to use it though:
module AnalogToUInt (a, b);
parameter WIDTH = 1;
inout [WIDTH-1:0] a; output [WIDTH-1:0] b;
assign b = a;
endmodule
module UIntToAnalog (a, b, b_en);
parameter WIDTH = 1;
inout [WIDTH-1:0] a; input [WIDTH-1:0] b; input b_en;
wire [31:0] z32;
assign z32 = 32'hZZZZZZZZ;
assign a = b_en ? b : z32[WIDTH-1:0];
endmodule
That works! Thank you very much.
This issue should be closed now.
BTW, can you help me with #144 ?
In order to fit sifve-inclusivecache, I bumped rocket-chip newer to bcb3d0a
However, when I build, it prompted that:
I find out that MaskROM has helper object attach instead of trait since #1698
Then I deleted that line, and another error surfaces:
How can I fix this?