Closed Tim453 closed 4 years ago
Hi, thanks for the contribution!
I tend to think that the reduced config was used because of area limitations on the Arty35 fpga. Have you tested this and had it fit fine?
Yes i have tested it, it works fine.
This is the utilization of the system with the TinyCore:
and this with the changes i have made:
The values may have changed between FE310-G000 and FE310-G002.
The values may have changed between FE310-G000 and FE310-G002.
Actually not, the manual says both Versions have a 16kb I-Cache and a btp. Even the device tree of the SDK says it has a 16kb I-Cache.
In that case, I'm okay making this change, though I have a few requests to clean up the code a bit
Looks good. Just to confirm, this configuration as is now fits fine on the arty?
Yeah, I tried, it fits.
The configuration of the TinyCore which is used in the TinyConfig, does not match with the Configuration, that is described in the FE310 Manual. The TinyCore has no branch target predictor and only a 4kb direct-mapped I-Cache.
This commit adds a btp and changes the I-Cache to a 16kb 2-way I-Cache