farzadfch
commented
6 years ago The IOFPGA+NVDLA design does not implement any RISC-V core and is supposed to be connected to HiFive Unleashed board via the FMC connector.
Closed isuckatdrifting closed 6 years ago
farzadfch
commented
6 years ago The IOFPGA+NVDLA design does not implement any RISC-V core and is supposed to be connected to HiFive Unleashed board via the FMC connector.
Hello guys,
I’ve been implementing Xilinx Ultrascale VCU118 (Sifive core + NVDLA) these days. I cloned the master branch of freedom and compiled using
Makefile.vcu118-iofpga-nvdla… the timing is -110ps, but I bypassed the final check and managed to generate the mcs file for the rom.On the Linux image side, I connected a flashed SDCard via PMOD to VCU118, not the slot on the board.
The question is that as I boot the FPGA from vivado hw server “boot from configuration memory device” or reboot the FPGA, there’s no UART info output but GPIO_LED0 and GPIO_LED1 are flashing (like ~1Hz). I guess the core is running because I saw from U500 guide that an LED blink demo should be running?
Is it because that I should change the scala file at
fpga-shells/src/main/scala/shell/xilinx/VCU118NewShell.scala? or the VCU118Shell.scala? There’s some pcie and ddr code in it. I’m just uncertain about it because generating mcs takes 8 hours…And after the I comment the lines 281-283 (about fmc, edge and ddr) in
VCU118NewShell.scala, vivado HW server is reporting thatDevice xcvu9p (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it., but the leds are still flashing and linux isn't booting.Hopefully some guys here could help me with this issue. Thanks a lot!