Open austinharris opened 4 years ago
I'm trying to build the VCU118 bitstream and I get a failure in Vivado for missing EICG_wrapper. I realize this verilog file is inside rocket-chip, but I'm having some trouble figuring out how to fix the wake rules to include the file.
Thanks!
I'm trying to build the VCU118 bitstream and I get a failure in Vivado for missing EICG_wrapper. I realize this verilog file is inside rocket-chip, but I'm having some trouble figuring out how to fix the wake rules to include the file.
Thanks!