Closed ubfx closed 2 months ago
Turning this into a draft while I experiment with how to best hand the files over to the simulator. I wanted to avoid merging all the cells into a single Verilog file (like it is also done for the LEFs) to keep the library close to the original. But it seems like keeping them all seperate will just make it more complicated for the simulation steps and also blow up the schema unnecessarily.
By the way, I noticed that the verilog views of the gf180 and asap7 PDKs are not listed in the schema, is there a reason for that? Could we put the Verilog file under the keypath 'output', 'verilog'
?
@ubfx a couple of things:
('output', 'rtl', 'verilog')
@gadfort Thank you for the pointers.
I removed all the unnecessary files. However, I think we still need two versions of every cell, the ones with power ports and the ones without. Having two different files and two different keypaths ('rtl', 'verilog'
and 'rtlpower', 'verilog'
) seems a little cumbersome though; so I implemented it by means of a ifdef
structure.
I realized that OpenPDKs already provides a merged version of the model files, using a similar ifdef
structure, so I moved over to using theirs instead of using our own merge-script. While the OpenPDK version might be a little worse to read because the license is replicated N times within the file, I think it's still better than adding another slightly different merged version of these files. Also it keeps the names of the Verilog defines (USE_POWER_PINS
and FUNCTIONAL
) consistent between lambdapdk and OpenPDKs.
This patch adds verilog cell models and UDPs unmodified from https://github.com/efabless/skywater-pdk-libs-sky130_fd_sc_hd/commit/89492a051231edb799c330208ed48542eb6a29d7. The source repository is also under Apache-2.0 license (https://github.com/efabless/skywater-pdk-libs-sky130_fd_sc_hd/blob/master/LICENSE) so an additional license notice should not be necessary.
Fix https://github.com/siliconcompiler/lambdapdk/issues/15