update list of fully implemented instruction sets

[Torinde]

"SSE4.1 List including CRC32" - I think the CRC32 instructions are some of the "non-SIMD" SSE4.2, not SSE4.1.

Related question is if SIMDe implements the non-SIMD instructions of MMX, SSE, SSE2, SSE3? From a cursory search I did it seems the answer is no.

Also, would you like to have Issues raised for:

• SSE4a, VPCLMULQDQ, VAES; FMA4 - those are the (still missing?) SIMD extensions for which I didn't see an Issue
• Bit manipulation instructions (BMI1, BMI2; ADX; ABM; TBM) - using VEX/XOP prefixes
• x87 (instructions list: current, obsolete Intel/IIT/Cyrix, obsolete NEC: part1, part2)
  • code is available in SoftFloat (QEMU, Berkeley)
  • useful even on x86, because x87 may get removed in a future x86 CPU (already deprecated in Windows, unsupported in MSVC)
  • POWER9, z, RISC-V Q/L support 128-bit precision, which may speedup emulating the 80-bit x87
  • relevant for DOS/Win9x/WinXP emulators

[mr-c]

Good catch, I'll split out CRC32 separately since our SSE4.2 support is incomplete.

And https://github.com/simd-everywhere/implementation-status/blob/main/x86.md#vpclmulqdq is implemented, so I'll add it to the list

Happy to have new issues for AVX512-VAES, SSE4a, FMA4 and others, sure. Please double check https://github.com/simd-everywhere/implementation-status/blob/main/x86.md in case it is already done, but not documented.

If you or your collaborators are interested in implementing some of these, we can have a video call where I can walk you through adding a new intrinsic implementation.

[Torinde]

OK, created a few Issues.

Looking at implementation status/x86.md:

• SSE Implemented: 239 of 241 (99.17%), but listed on the main page as complete
• AVX Implemented: 296 of 298 (99.33%), but listed on the main page as complete
• CLMUL - only 1 of 5 instructions is implemented, but x86.md lists only that one (PCLMULQDQ) so it shows 100%
• XOP - not listed in x86.md
• SVML - some instructions are listed in x86.md under AVX, SSE, etc. (probably as expected since SVML isn't an "instruction set" per se?)
• WebAssembly SIMD128 - no .md file in implementation status
• BMI1 is partially listed, but non not fully and also not BMI2 and ADX (although both are present in Intel Intrinsics Guide); SSE3 non-SIMD is partially listed (MONITOR, MWAIT); POPCNT is listed; In general I'm not sure how to check if the following are implemented/if I should raise Issues for the following?
  • non-SIMD instructions related to
  • MMX (FXSAVE(64), FXRSTOR(64), RDPMC),
  • SSE (PREFETCHNTA, PREFETCHT, SFENCE),
  • SSE2 (LFENCE, MFENCE, MOVNTI, PAUSE, CLFSH),
  • SSE3 (MONITOR(X), MWAIT(X), FISTTP),
  • SSE4a/4.2 (POPCNT, LZCNT, which are the same as ABM)
  • MMX instructions introduced with
  • SSE,
  • SSE2,
  • SSSE3
  • Bit manipulating extensions
  • BMI1,
  • BMI2;
  • ADX;
  • TBM # Readme file has a section about hardware architectures tested in CI, but in ci.yml I see more - should the following be specified in the README.md?
• Loongson is ran only at 64-bit (and not 32-bit)?
• PPC64 is ran as both little endian and big endian?
• RISC-V 64-bit without RVV and with RVV 128/256/512-bit - #1145?
• WebAssembly SIMD128 - Emscripten 32-bit and 64-bit, fixed and relaxed?
• Zarchitecture ZVECTOR ?
• in simde-features.h there is also ARMv8 SVE, but I couldn't find it in ci.yml?

[mr-c]

• SSE Implemented: 239 of 241 (99.17%), but listed on the main page as complete
• AVX Implemented: 296 of 298 (99.33%), but listed on the main page as complete

See https://github.com/simd-everywhere/simde?tab=readme-ov-file#caveats

Please create issues or PRs for the others, thanks!