MMX/SSE related functions

[Torinde]

Per https://github.com/simd-everywhere/simde/pull/1152#issuecomment-2021047051 - listing those in case some of them are not yet implemented.

non-SIMD instructions related to:

• P5
  • [ ] CL1INVMB (SCC only)
• MMX
  • [ ] FXSAVE(64) _fxsave64
  • [ ] FXRSTOR(64) _fxstore64
  • [ ] RDPMC _rdpmc
• P6 (between MMX and SSE)
  • [ ] CMOVcc reg,r/m 0F 4x /r Conditional move to register. The source operand may be either register or memory.
  • [ ] NOP NOPL r/m NFx 0F 1F /0 Official long NOP.
  • [ ] SYSCALL 0F 05 Fast System call.
  • [ ] SYSRET 0F 07 Fast Return from System Call. Designed to be used together with SYSCALL.
  • [ ] SYSENTER 0F 34 Fast System call.
  • [ ] SYSEXIT 0F 35 Fast Return from System Call. Designed to be used together with SYSENTER.
• SSE
  • [x] PREFETCHNTA a.k.a _mm_prefetch Already implemented as simde_mm_prefetch
  • [x] PREFETCHT (see above)
  • [x] SFENCE _mm_sfence Already implemented as simde_mm_sfence
• SSE2
  • [x] LFENCE _mm_lfence Already implemented as simde_mm_lfence
  • [x] MFENCE _mm_mfence Already implemented as simde_mm_mfence
  • [x] MOVNTI _mm_stream_si{32,64} Already implemented as simde_mm_stream_si{32,64}
  • [x] PAUSE _mm_pause Already implemented as simde_mm_pause
  • [x] CLFSH _mm_clflush Already implemented as simde_mm_clflush
  • [ ] FS: Jcc 64 (70..7F) rel8, 64 0F (80..8F) rel16/32 On Intel NetBurst (Pentium 4) CPUs, the 64h (FS: segment) instruction prefix will, when used with conditional branch instructions, act as a branch hint to indicate that the branch will be alternating between taken and not-taken. Unlike other NetBurst branch hints (CS: and DS: segment prefixes), this hint is not documented. Available on NetBurst CPUs only. Segment prefixes on conditional branches are accepted but ignored by non-NetBurst CPUs.
  • [ ] HWNT / HST branch hints
• SSE3
  • [ ] MONITOR _mm_monitor implementation-status,
  • [ ] MWAIT _mm_mwait implementation-status
  • [ ] FISTTP
• SSSE3
  • [ ] MOVBE intrinsics
• SSE4.1
  • [ ] XSAVE(64), XRSTOR(64), XGETBV, XSETBV intrinsics
• SSE4a/4.2 - ABM
  • [ ] POPCNT _mm_popcnt_u{32,62} and _popcnt{32,64} implementation-status,
  • [ ] LZCNT _lzcnt_u{32,64}

MMX instructions introduced:

• with SSE
  • [x] MASKMOVQ implemented as _mm_maskmove_si64, _m_maskmovq
  • [x] MOVNTQ implemented as _mm_stream_pi
  • [x] PSHUFW implemented as _m_pshufw, _mm_shuffle_pi16
  • [x] PINSRW implemented as _mm_insert_pi16, _m_pinsrw
  • [x] PEXTRW implemented as _mm_extract_pi16, _m_pextrw
  • [x] PMOVMSKB implemented as _mm_movemask_pi8, _m_pmovmskb
  • [x] PMINUB implemented as _mm_min_pu8, _m_pminub
  • [x] PMAXUB implemented as _mm_max_pu8, _m_pmaxub
  • [x] PAVGB implemented as _mm_avg_pu8, _m_pavgb
  • [x] PAVGW implemented as _mm_avg_pu16, _m_pavgw
  • [x] PMULHUW implemented as _mm_mulhi_pu16, _m_pmulhuw
  • [x] PMINSW implemented as _mm_min_pi16, _m_pminsw
  • [x] PMAXSW implemented as _mm_max_pi16, _m_pmaxsw
  • [x] PSADBW implemented as _m_psadbw, _mm_sad_pu8
• with SSE2
  • [x] PADDQ implemented as _mm_add_si64
  • [x] PSUBQ implemented as _mm_sub_si64
  • [x] PMULUDQ implemented as _mm_mul_su32
• with SSSE3
  • [x] PSIGNB implemented as _mm_sign_pi8
  • [x] PSIGNW implemented as _mm_sign_pi16
  • [x] PSIGND implemented as _mm_sign_pi32
  • [x] PSHUFB implemented as _mm_shuffle_pi8
  • [x] PMULHRSW implemented as _mm_mulhrs_pi16
  • [x] PMADDUBSW implemented as _mm_maddubs_pi16
  • [x] PHSUBW implemented as _mm_hsub_pi16
  • [x] PHSUBSW implemented as _mm_hsubs_pi16
  • [x] PHSUBD implemented as _mm_hsub_pi32
  • [x] PHADDSW implemented as _mm_hadds_pi16
  • [x] PHADDW implemented as _mm_hadd_pi16
  • [x] PHADDD - mnemonic missing in Intel intrinsics list, but implemented as _mm_hadd_pi32, which appears under PHADDW
  • [x] PALIGNR implemented as _mm_alignr_pi8
  • [x] PABSB implemented as _mm_abs_pi8
  • [x] PABSW implemented as _mm_abs_pi16
  • [x] PABSD implemented as _mm_abs_pi32

[mr-c]

Many of the rest are already implemented in SIMDe. I updated the table to add the intrinsic names next to the CPU instruction mnemonic.

[mr-c]

@Torinde Can you add the intrinsic/function name for the rest of the instructions? I'm seeing more of then as already implemented in SIMDe

Thanks for flagging these, we need to represent this status information better in our docs

[Torinde]

Can you add the intrinsic/function name for the rest of the instructions? I'm seeing more of then as already implemented in SIMDe

How do you check?

[mr-c]

Can you add the intrinsic/function name for the rest of the instructions? I'm seeing more of then as already implemented in SIMDe

How do you check?

1. Go to https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#
2. Search for the instruction name: https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=MASKMOVQ
3. If there are multiple hits, check them for a matching Instruction: line: https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=MASKMOVQ&ig_expand=4253 → _mm_maskmove_si64
4. Check SIMDe source for the intrinsic: https://github.com/simd-everywhere/simde/blob/517da845ac83098d06c5b0c9d8705ac8eb32a5ba/simde/x86/sse.h#L2922-L2942

Thanks!

[Torinde]

Done - remaining instructions I don't find in Intel intrinsics list.

Most are implemented, only 14 "related" ones aren't.