some questions about this library

[dangerggg]

Hello! How can I deal with the input and output if I want to use this in my FPGA? I tried to plan the pin but the data line is always high, is there any input required? Thanks a lot!

[dangerggg]

By the way, what's the function of input pb?

[simon-77]

Dear dangerggg

I have developed a 'piggy-pack' with 4 pushbuttons (input pb), an SD-Card socket and a few LEDs for the FPGA development board "Altera DE0-Nano". The top-level architecture 'sd_v3_a' was developed for testing purpose. It instantiates the entity 'simple_sd', which is the entity you have to instantiate to use the library.

The buttons were used to: pb(0): reset the software pb(1): read a single block pb(2): read multiple blocks pb(3): stop the 'read multiple blocks' operation

To use this top-level arichtecture 'sd_v3_a' you have to provide a clock-signal on pin 'clk' and use normal push-buttons (with pull-up resistors) to start the read operation.

Kind regards Simon

[dangerggg]

Dear Simon

Sorry for my late respond due to my disgusting finals... If I want to use this library in my project, what should I do(I want a high-speed transfer mode to suit my VGA)? I am a green hand in FPGA programming and I only learned some basic grammars from my teacher, I am so glad that you are willing to help me! You have said that I can use normal push-buttons to control the pb, it doesn't work when I set the pb in the process(code), why?

ps:My FPGA is not an Altera DE0-Nano version, does it mean that I can't use this library？ Thanks a lot!

Kind regards dangerggg

[simon-77]

Dear dangerggg

this VHDL Library does not use any specific IP-cores from Altera. Just ordinary VHDL is used, thus the Library can be implemented on any FPGA.

If you want to use the Code just consider the source files in 'VDHL-SD-Library/sd_v3/source/'. Include the three directories with all source files in your project, change the constants in 'de0_nano/de0_nano_const_pkg.vhd' according to your concrete setup and instantiate the entity 'sd_pkg.simple_sd' to use the VHDL-SD-Library.

The file 'sd_v3.vhd' is my top-level architecture and works as a testbench for using the VHDL-SD-Library. Just have a look inside this source file to see how the VHDL-SD-Library can be used.

Kind regards Simon

[Madesh12]

where i have to get the board pin details(user constraints file) that you used in your project

[simon-77]

where i have to get the board pin details(user constraints file) that you used in your project

Do you mean the "Synopsis Design Constrains": sd_v3/source/de0_nano/SynopsysDesignConstrains_DE0-Nano.sdc

or Quartus *.qsf file: sd_v3/sd_v3.qsf

• The first one (.sdc) sets the time constrains to tell the synthesiser how fast the logic has to be. For example it tells Quartus that the signal "clk" will change it's state with 50 MHz.

The .sdc file I use is a combination of the official example .sdc file from the manufacturer Altera, Alteras documentation and some input from other users.

• The second one (.qsf) gives Quartus information about the project. For example which FPGA-Chip is used (EP4CE22F17C6), where the source files are and it also assigns VHDL signal names to actual pins of the IC.

set_location_assignment PIN_R8 -to CLK for example assigns the VHDL-Signal name "CLK" to the pin "R8" of the IC. You find the pinout of the IC in the datasheet.

[Madesh12]

i am going to use your project for edge artix 7 board

On Fri, May 31, 2019 at 6:55 PM Simon notifications@github.com wrote:

where i have to get the board pin details(user constraints file) that you used in your project

Do you mean the "Synopsis Design Constrains": sd_v3/source/de0_nano/SynopsysDesignConstrains_DE0-Nano.sdc

or Quartus *.qsf file: sd_v3/sd_v3.qsf

• The first one (.sdc) sets the time constrains to tell the synthesiser how fast the logic has to be. For example it tells Quartus that the signal "clk" will change it's state with 50 MHz.

The .sdc file I use is a combination of the official example .sdc file from the manufacturer Altera, Alteras documentation and some input from other users.

• The second one (.qsf) gives Quartus information about the project. For example which FPGA-Chip is used (EP4CE22F17C6), where the source files are and it also assigns VHDL signal names to actual pins of the IC.

set_location_assignment PIN_R8 -to CLK for example assigns the VHDL-Signal name "CLK" to the pin "R8" of the IC. You find the pinout of the IC in the datasheet.

— You are receiving this because you commented. Reply to this email directly, view it on GitHub https://github.com/simon-77/VDHL-SD-Library/issues/1?email_source=notifications&email_token=ALC6KZTZMAEVZDNUKYTDUEDPYERK7A5CNFSM4FEHXQ22YY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGODWVGUGA#issuecomment-497707544, or mute the thread https://github.com/notifications/unsubscribe-auth/ALC6KZUNKXXUABH3JUA7LDLPYERK7ANCNFSM4FEHXQ2Q .

[simon-77]

I don't have experience with XILINX but my sd-card library is generic VHDL and should work with this FPGA too.

If you have any questions about my library feel free to ask and please keep me posted.

[Twister10000]

Hello Simon many thanks for your great SD-Card Library Why did you arrange the data in an array? Better said how did you read the array efficiently. If I write out each index individually I “burn” a lot of Logic Elements unnecessarily

I would be very happy about an answer Kind regards from Switzerland

Twister10000

[simon-77]

Hi @Twister10000

Fair point, using the dat_block_type as output signal is definitely not the most efficient way of implementing a data interface.

This was the first "larger" VHDL project of mine and was part for my final thesis of higher technical school (HTL in Austria). One the one hand my intention was to have a "simple" and "generic" interface (platform independant / without using IP cores for memory) and on the other hand, we were working on a pretty large FPGA (some Intel / Altera MAX 10) and had no issue synthesising this design for our platform.

Regarding you question of using the data: In our implementation we where required to have a "large" buffer (~ 50 kB) for the incomming SD-Card data stream. We utelised an Memory IP-core for this larger buffer and I then had another VHDL unit, which sequentally read the dat_block_type output array byte for byte and wrote the content into the IP-memory.

When you have troubles implementing my SD-Library onto your hardware, it should not be too hard to modify the vhdl interface (ports) to your specific implementation (e.g. instead of an array, having data, address & wr_ena ports going into some sort of memory):

• The transceiver writes to the output array only in state s_read https://github.com/simon-77/VDHL-SD-Library/blob/4834800ae29809b3b17ad309be057b7852f79824/sd_v3/source/sd/sd_transceiver.vhd#L738
• And the controller is only using the smaller status_reg, which you could probably simply add as additional port from the transceiver to the controller, without burning too many logic cells https://github.com/simon-77/VDHL-SD-Library/blob/4834800ae29809b3b17ad309be057b7852f79824/sd_v3/source/sd/sd_controller.vhd#L336

So I hope you can work around this shortcomming somehow - let me know when you need further help with this library, or when you have successfully used it.

Kind regards from Austria Simon