sinara-hw / DIO_SMA

DIO_SMA 8 channel isolated digital input/output EEM
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Fast output rise time causes unexpected termination FET turn on #13

Closed TopQuark12 closed 3 years ago

TopQuark12 commented 3 years ago

Under guidance from @sbourdeauducq , it was discovered that a combination of fast output rise time and variation in the BSS138L parasitic capacitance and turn-on voltage, may cause an unexpected turn-on on some BSS138L termination FETs during output switching.

This effect causes a weird slope to appear towards the top of the pulse that lasts for ~1us, and is more pronounced when driving unterminated loads. Even on output channels that do not exhibit this issue, measuring the Vgs of the FETs shows the margin between the output working as expected and the issue showing is very slim.

In the below screenshots, the yellow trace shows the output connected to scope with 50cm coax and with 1M input termination. Blue trace is the Vgs of the BSS138L FET.

The issue on failed output channels: Bad fet 1M

Output on "good" channels, but Vgs shows it is marginally working: Good fet 1M

Adding a 1nF cap across gate and source of the FET fixes the issue. image-42236a04-afd5-4574-a813-a7ec35c39a57

After

hartytp commented 3 years ago

good catch!

sbourdeauducq commented 3 years ago

Does it improve the situation on those cards where the effect is not so pronounced, e.g. https://github.com/sinara-hw/DIO_SMA/issues/4#issuecomment-841132777 ?

TopQuark12 commented 3 years ago

It does!

Before (Vgs not measured, probing it changes the output signal on this channel): SDS2504X Plus_PNG_39

After soldering 1nF cap: SDS2504X Plus_PNG_40

gkasprow commented 3 years ago

Does it exist in the boards where the resistor between G and S was installed to eliminate the previous issue related to signal edges (https://github.com/sinara-hw/DIO_SMA/issues/4)?

sbourdeauducq commented 3 years ago

Yes. And if you look at the duration of the disturbance it's in the ballpark of the RC product of that resistor with the gate capacitance.