Closed ghost closed 3 years ago
Odd. I’ve never seen anything like that. Do you have the termination switches on?
If you have access to the hw can you stick a scope in a few places down the signal path (from lvds buffer to output) and see where this effect originated? Also worth checking nothing funny is going on with the supplies.
Don't you have AC coupling turned on in your scope?
Are you using a scope probe or connecting the signal directly in to the scope?
Don't you have AC coupling turned on in your scope?
The other thing I did wonder about was if this is related to the AC-coupled grounds. Depends whether an isolated power supply is used in the apparatus.
A follow-up to the original forum report indicates that this also happens on DIO-BNC. (I've never seen anything like that on ours, though.)
It looks like some AC-coupling effect. Could be scope ground connected to one of four upper IOs and the signal observed on one of 4 lower outputs wi
Dear all,
Thank you for the replies. I've just used the oscilloscope again, using DC coupling and a 10x probe, connecting to the ground of the SMA head that is under test. However, the same shape of the rising edge is there.
Edit: In reply to @hartytp, the termination switches are all off.
Thank you for the replies. I've just used the oscilloscope again, using DC coupling and a 10x probe, connecting to the ground of the SMA head that is under test. However, the same shape of the rising edge is there.
I don't follow you here...do you mean the tip of the probe was connected to the SMA ground (in which case, where was the probe ground connected)? Or, do you mean that the probe tip was connected to the SMA centre pin and the probe ground was connected to the SMA ground?
Can you try connecting the probe ground to the PCB ground instead of the SMA ground?
Can you connect the second channel of the scope to the 5V supply of the driver IC?
Hi,
I'm here to report the same issue with our SMA-DIO. I also tested with/without termination switch on.
I saw a similar rising edge without termination switch on, while there was no similar rising edge is happening with the switch on. The problem with the switch is that it lowers high voltage levels from 3.6V to 2.4V, not sufficient to trigger the device we have.
Here's the picture of an oscilloscope:
the scope was DC-coupled, and when I add a tee and 50ohm termination, the voltage rise was sharp again but the output voltage was 1.8V, half of 3.6V.
Can you connect the second channel of the scope to the 5V supply of the driver IC?
I checked two test points on the board:
5.554V and 5.528V, seems reasonable.
measured 5V (ch2) while sending pulse (ch1, 1.5ms width)
OK, this looks very intriguing. I asked my student to recreate it with exactly the same setup as yours. Hopefully, tomorrow we will be able to check what is going on.
In the past, I observed very strange behavior of the transceivers. They seemed to be sensitive to light (sic!). Their high level was dependent on whether I shined strong IR light from incandescent lamp or not. It did not work with visible LED light. It does not explain the issue you are reporting but can be related.
We recreated the issue. I loaded 2 outputs with 50R and observed power supply. There is 50mV drop with small ripples
The input signal looks fine. The output issue is the same even with 50Ohm termination. I can also confirm that a high level depends on lighting conditions. Set output H, turn on the strong LED light (I used my mobile phone), observe ~500mV change in the output voltage. Here is the behavior. Output terminated with 50Ohm. The pattern was created by moving the phone above the board. This is not EMI from phone, the same effect is created by keeping the LED lamp and obscuring the light path.
The light sensitivity of the silicon IC is nothing new. I'm surprised that the black opaque package still leaks enough light that produces a measurable effect. I wouldn't connect these to effects.
Is this the LVDS-CMOS converter or the isolator? The isolator should be magnetic coupling not optical, right?
With 50ohm, the high level is around 2V. Isn't it unacceptable? This is what I read from this github page:
Outputs can supply 5V into 25Ohm, and can tolerate an indefinite short-circuit to ground.
It is just the TTL buffer chip. We have 30Ohm in series with a 25built-in resistor. It looks like we have to lower the resistor to ensure at least 2.1V in H state.
The wiki suggests that the card would output 5V when connected to a 25-ohm resistor. If that's incorrect or misleading, it should be edited.
That's right. I replaced it with statement: Outputs can supply valid TTL level into 50Ohm load
And it's only 12.5 Ohm + 30 Ohm since we take two in parallel.
That's right. I replaced it with statement: Outputs can supply valid TTL level into 50Ohm load
I'm not sure. I'm certainly not electronics guy, but I was thinking ttl high should be either 3.3V or 5V. and less than 2V with 50ohm (or even with 2.1V high) doesn't satisfy any of them.
TTL does not care about the load. Input levels are the same. 50R load is used to match the impedance only, mainly for long cables. TTL input H is >2V and L is <0.8V. The same with LVTTL, that's why in TTL world you can safely connect 3.3 and 5V domains, which you cannot do in the CMOS world. So 2V still meets the specification of H state. The surprising fact is that with 30+12Ohm : 50Ohm divider we almost get 2V at the beginning of the pulse train. Later on, we get nearly 2.5V at the end of the pulse train, without changing the supply. The same amplitude change happens when we use non-terminated output but the value is higher. I have one suspicion that needs to be verified. The two drivers are connected in parallel. This means that during the transition state, the skew causes cross-condiction and momentary short circuit which generates a ground bounce. However, this does not explain why after a series of pulses the circuit works properly. Maybe it heats and changes the propagation delay...
Another idea is that we use ICs from some weird series with some bugs. I will order one from another source and give it a try.
TTL does not care about the load. Input levels are the same. 50R load is used to match the impedance only, mainly for long cables. TTL input H is >2V and L is <0.8V. The same with LVTTL, that's why in TTL world you can safely connect 3.3 and 5V domains, which you cannot do in the CMOS world.
I think I've got your point, couldn't understand 100% though.
So my issue is, it can be out of focus though, if I were to trigger another device that needs at least ~4V high to trigger, how can I use sma-dio to do that? it can be triggered without impedance matching (>>50ohm), but the rising edge leads very long and indeterministic delay (~1ms +- 100us).
You can put a terminator and use a comparator or other kind of TTL receiver that would trigger at ~2V and output 5V next to the target device. The wire length between the TTL receiver and the target device can be short so there are no issues with transmission line effects.
The DIO modules have series termination, so if your module has hi-Z input, you can use it without termination and still preserve the pulse shapes. I ordered the transceiver ICs from other source and will test them. I have a suspicion that existing ones come from unauthorized source, even though they were bought from trusted vendor. I already met a few times fake ICs with much worse parameters than specified. The TI logo on the chips I have look suspicious.
The ICs I ordered have a different logo and markings than the ICs that cause problems. I will swap them and see if that helps.
Hi. We've been having the exact same issue. We found this behavior connecting the output directly into a scope (TBS2000). Same thing using a Red Pitaya with a 10x scope probe and also with sma-sma Mini-Circuits attenuators.
Each pulse after a long period of ground state gets this same rising edge situation. After the initial skewed edges it seems to stabilize and works correctly for every pulse afterwards.
OK, I found the issue. It's charge build-up on the termination FET. When I touch the FET gate with scope probe the problem disappears. I suggest adding 10k resistors between G and S of all termination FETs.
It also explains light sensitivity - it's LED that behaves as a solar cell and opens the termination FET :) Thanks @marmeladapk for discovery of this effect
Good find!
I suggest adding 10k resistors between G and S of all termination FETs.
Has this been tested and should we rework the existing boards accordingly?
Today, I tested a DIO_SMA v1.1 again and reproduced the problem, with slight difference in the edge shape. For simplicity, I only carried out tests to only call t4()
on a TTL output channel. Below shown is the trace before doing any rework:
Then, we reworked the board by adding the 10k ohm resistor across each of the termination LEDs. After rework, the issue has been confirmed to be fixed. Plus, shining those LEDs with strong light (e.g. phone flashlight, laser pointer) do not change the voltage waveform. Below shown is the trace after rework:
Hi to all! Using Greg's fix (link), we can no longer find rising edges that last several microseconds. But recently I have observed a similar behaviour on a shorter time scale. The difference is that the rising edge last for ~200ns instead. This seem to occur only on some units of v1.2 from TechnoSystems. Attaching oscilloscope screenshots as follows:
IO0:
IO4:
Unlike the problem I found in the past, this is not negatively impacting DIO accuracy or performance, and it might not be a problem at all. I would appreciate if anyone would know an explanation. Thank you!
The TTL standard defines a valid H level as above 2.1V. So this still conforms to the standard. The buffers we use are CMOS devices and they can be non-linear close to the rails. How long is your cable? Is It terminated?
@gkasprow Thank you for the feedback and info about the TTL standard.
The cable is around 30cm long. It is an SMA coaxial cable where one end is connected to an SMA-BNC adapter for the oscilloscope, and the other end is connected directly to the SMA of the TTL channel. We set the oscilloscope in 1M ohm impedance. We didn't use any additional terminators.
Think the issue is just impedance mismatch in test setup, see the screenshots with 1M input impedance vs 50 ohm input impedance.
Issue description
A user of ARTIQ reported an issue about an obvious rising edge when the DIO generates 5-ms pulses. I was able to reproduce the same oscilloscope output as him, which is: Fig. 1: TTL4 output on an oscilloscope.
On the other hand, the rising edge of a longer pulse (400 ms) looked like this: Fig. 2: TTL5 output on an oscilloscope.
Steps to reproduce the issue
Expected result
The rising edge of a pulse of any length on a TTL output should be sharp under this magnification (10 ms per grid).
CC: @sbourdeauducq