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Semiconductor diode laser current driver
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Noise/ripple on the Stabilizer MCU ADC inputs #15

Open nkrackow opened 1 year ago

nkrackow commented 1 year ago

I was wondering why the readings on the current and voltage readbacks are relatively noisy: Screenshot from 2022-12-29 11-26-11 This is clear for the HP current channel #13, but the voltage readings should be using quite some dynamic range of the ADC. I first suspected the software/ADC setup procedure since we had problems with this in the past https://github.com/quartiq/stabilizer/issues/571 https://github.com/stm32-rs/stm32h7xx-hal/issues/374

However, I am now quite certain this is actual electrical noise on the nodes. The samples of the ADC look like this and have about 1000 LSB PP (~1.5% fullscale) and 240 LSB RMS noise. Figure_2

I made a small 50:50 resistor divider between GND and 3V3 directly on the Stabilizer ADC header with the 1.65 connected to an ADC input. Now I see much less noise of ~100 LSB. Figure_1

I cant measure the noise on a multimeter but I can see significant ripple on the scope. Ofc noise is difficult to measure accurately and I just used a standard probe with an alligator GND lead (loop). This is directly on the connector pin that goes to stabilizer and that represents the LN output voltage: Screenshot from 2023-02-16 18-09-24 Frequency of the ripple is about 50 kHz. (sorry for the missing x axis)

The LN current measurements look much cleaner too: Figure_3 45 LSB RMS and the pin looks much cleaner on the scope too: Screenshot from 2023-02-16 18-35-05

Sampling was at 200 Hz with sampling time for one sample 2 ADC cycle times. This means most of the time the ADC was not sampling anything and the noise bandwidth is much higher than the signal bandwidth. Ofc. the 50 kHz ripple are not directly visible on the ADC like this.

The ADC sampling time (in the standard driver code at 810 ADC cycles) has an effect on the noise to about 64 cycles. Longer sampling times don't bring any benefit, at least not with the amount of electrical noise I was seeing anyways.

gkasprow commented 1 year ago

can you make FFT of adc record ?

nkrackow commented 1 year ago

The problem is that the ADC samples very fast (it could run at 100 kHz of faster) but does so only at a rate of 200 Hz. So I'm not sure what exactly to make of the spectrum: Figure_fft This is the PSD of the data with 1000 LSB PP (~1.5% fullscale) and 240 LSB RMS noise. Normalized to the sample rate, so 0.5 is 100 Hz.

nkrackow commented 1 year ago

Getting the ADC to sample much faster would require quite substantial changes to the software right now..

gkasprow commented 1 year ago

Can't you just read the ADC as fast as possible filling entire RAM and then dump them to UART?

nkrackow commented 1 year ago

Well yes but I'd have to write quite some code for that ;)

nkrackow commented 1 year ago

Could you guys at Creotech (I think @bbradzik has the other Driver right?) check if you see the 50 kHz ripple on the voltage sense nodes? CS_OUT_MON_LN and CS_OUT_MON_HP on the schematic.

bbradzik commented 1 year ago

I didn't noticed anything like that.

But sure, I will check that again.

What amplitude to expect ?

Under what load and DAC code does it appear?

nkrackow commented 1 year ago

Maybe one more piece of evidence from the subsampled ADC data is the histogram:

Voltage: histo_voltage Voltage histogram from scope: Screenshot from 2023-02-21 09-38-47 Current: hist_current Current scope: Screenshot from 2023-02-21 09-48-52

Not perfect but definitely the same skew from the asymmetric ripple in the statistics.

Also the magnitude of the voltage ripple relative to the ADC fullscale and magnitude of the noise in the ADC samples is in rough agreement.

nkrackow commented 1 year ago

Sorry, forgot about your questions @bbradzik.

What amplitude to expect?

Around 20 mVpp as in the scope screenshot.

Under what load and DAC code does it appear?

That was with 100 mA load into a normal diode. But the noise is always there.

bbradzik commented 1 year ago

The P1V5REF voltage is oscillating due to wrong output capacitor selection (red dot shows present situation):

tlv_osc

Adding 10uF/6.3V X7R MLCC capacitor across C89 on top layer kills the 50kHz oscillations. However there is still one problem: the P1V5REF rail is still not clean because of the ripple coming from P12V0 power line. I will prepare the simplest solution to that.

nkrackow commented 1 year ago

Cool, yeah the voltage readings look a lot better now (jump from 0 to 100 mA over two diodes)

The remaining noise seems to be more infrequent. Probably switching noise coming through from somewhere as you said.