clock distribution

[gkasprow]

I plan to use clock distribution IC with LVCMOS outputs. Clock input would be selectable:

• Carrier FMC CLK3 BIDIR, where DRTIO recovered clock is present
• 125MHz onboard generator, either 125MHz oscillator or delivered by clock chip PLL
• external clock input delivered by MMCX front panel input

[gkasprow]

Clock would be delivered to the following circuits:

• 8 x to DACs
• 4 x to FPGAs (2x LA, HA, HB)
• 1 x FMC CLK1 to enable further distribution in multi-board scenario

[gkasprow]

There are several clock ICs that fit requirements. Examples are:

• LMK03806
• AD9522

[gkasprow]

the ICs above won't work. We need 1.8V LVCMOS. The ADCLK854 seem to fit better

[gkasprow]

I can add Si549 oscillator as the on-board clock source

[gkasprow]

the ADCLK854 can be confgured as 16 LVCMOS outputs + 4 LVDS outputs. We need LVDS to route to FMC CLK inputs

[dhslichter]

I like this part (especially because there are no registers to program!) For the clocking, we need to ensure that the FPGA carrier board has the method to properly recover a high-quality clock from DRTIO (you are doing this already for other projects, right?), because this is the most likely thing that people will do. Si549 is useful for debug or some stand-alone testing.

[gkasprow]

the clock distribution

[gkasprow]

the new revision of AFC and DIOT carrier have already DRTIO clock recovery. Moreover, we can use SI549 as a part of digital PLL. External clock is also possible.