There is strong capacitive coupling between P12V0 plane on P4 layer and clean analog supply polygons on adjacent P3 and BOTTOM layers (P3V3A, P5V0A and N3V0A).
For assumed PCB stack-up and areas of polygons on P3 and BOTTOM the coupling to P12V0 reach the level of even dozens of pF.
Recommendation: split the P12V0 plane on P4 layer and connect to GND the areas under/upper supply polygons on P3/BOTTOM.
There is strong capacitive coupling between P12V0 plane on P4 layer and clean analog supply polygons on adjacent P3 and BOTTOM layers (P3V3A, P5V0A and N3V0A). For assumed PCB stack-up and areas of polygons on P3 and BOTTOM the coupling to P12V0 reach the level of even dozens of pF.
Recommendation: split the P12V0 plane on P4 layer and connect to GND the areas under/upper supply polygons on P3/BOTTOM.