HW issues - Githubissues

sinara-hw / FMC_Shuttler

16-channel 125MS/s 16bit DAC in FMC form factor.

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HW issues #30

Closed gkasprow closed 3 months ago

gkasprow commented 1 year ago

[x] Missing fiducials on PSU board
[x] Add 12V / GND testpoints on PSU board
[x] PGFB must be 3.2V ;
[x] R11=10k or 11k
[x] R2=33k
[x] R6=22k ?
[x] R15=47k?
[x] R7=100R

gkasprow commented 1 year ago

[x] check PGFB on AFE board and correct resistors

tprzywoz commented 1 year ago

[x] OSC1 should be connected to the same voltage level as VADJ
[x] OSC1 default variant is LVDS type - LVPECL resistors should be toggled to not fitted. It may fix #33 - MCX clock input was tested and works well.
[x] OSC1 and IC3 - Si53340 with VDD=1.8V is not capable to receive LVPECL signal (according to DS). VDD should be connected to 2.5 V or R12 R13 (LVPECL resistors) should be removed.
[x] no variant for FMC_REF_CLK: R54 R55 or R56 R57 should be toggled to not fitted.

kaolpr commented 1 year ago

In current revision (v1.1rc1) there is an assembly variant to connect OSC1 either by VADJ_BUF or P1V8A. Following note on the top sheet, the only supported VADJ is 1.8V. If this is our design assumption, which AFAIK is a completely valid assumption when designing FMC module, what for is that assembly variant included?

kaolpr commented 1 year ago

OSC1 and IC3 - Si53340 with VDD=1.8V is not capable to receive LVPECL signal (according to DS). VDD should be connected to 2.5 V or R12 R13 (LVPECL resistors) should be removed.

It is marked as done, but R12 and R13 are marked DNP only in variant. If we assume that VADJ is always 1.8V then those can be removed instead of DNP.