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sinara-hw / FMC_Shuttler

16-channel 125MS/s 16bit DAC in FMC form factor.
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Shuttler schematic review #6

Closed tprzywoz closed 3 years ago

tprzywoz commented 5 years ago

I've just published schematics of Shuttler. I know that Sayma review must be done first to start Shuttler review, but I will be grateful for checking compliance with the expected specification - I want to finish my master's thesis as soon as possible :)

gkasprow commented 4 years ago

@tprzywoz Is this the last version of schematics? I want to introduce some changes and also do the review.

tprzywoz commented 4 years ago

No, I changed the organization of FPGA schematics and fixed Sayma 2.0 issues that also affected Shuttler. I still have to finish some details. I'm going to push new version tomorrow.

tprzywoz commented 4 years ago

I published the last version. What changes do we want to make? My questions about potential changes: As I understand a direct PORT0 connection to GTH is already working. Can we remove ETH_PHY? / Do we want to wait for Sayma 2.0 to be sure? Same question about Exar module.

gkasprow commented 4 years ago

Let's leave as it is now. Do we miss some GPIOs?

tprzywoz commented 4 years ago

If we want to implement EXT_CLK_IN / WR_REF_CLK_IN connected to FPGA then we need more IOs. Also I thought about digital signals to control external AFE. Currently, we have 10 x 1.5V single-ended lines. We could add 3.3V lines without PHY.

gkasprow commented 3 years ago

not relevant since we moved to FMC