Shuttler DAC parallel LTC2000 connection

[tprzywoz]

I'm leaving results for future discussion.

As @gkasprow mentioned in #253 I made simulations for different FPGA output standards to check if it is possible to connect parallel LTC2000 (with internal LVDS termination) working with 150 MHz clock.

First configuration was 4 DAC to 1 IO bank of Artix-7. Only BLVDS standard meets the requirement of input voltage range (min +/- 200 mV). With 3 DAC we can use also SSTL18.

Example of schematic with 3 DAC

BLVDS simulation. Bit rate 600 Mbps.

SSTL18 simulation. Bit rate 450 Mbps

[hartytp]

This is very cool work, but it's covered by #253