Closed pathfinder49 closed 3 years ago
@pathfinder49 use variants to mark components as DNP
all components have a dedicated layer (M15) which can be used as a clearance indicator
all components have a dedicated layer (M15) which can be used as a clearance indicator
Are these minium requirements? For capacitors, the markings are much larger than the footprint.
Ace, thanks @pathfinder49 !
@gkasprow are you okay to do a careful review of the new layout, paying close attention to SI and cross-talk? Once that's done I'd love to get a new batch into production
@pathfinder49 btw https://help.github.com/en/enterprise/2.16/user/github/managing-your-work-on-github/closing-issues-using-keywords is a really nice feature to ensure the resolved issues get closed automatically when the PR is merged.
all components have a dedicated layer (M15) which can be used as a clearance indicator
@gkasprow The component clearences inbdicated on M15 tend to be rectangular. This does not match the actual component shpes. For example: the the 16 DAC pins leave the corners of the DAC clearance box physically un-occupied. Are these required to be unoccupieed?
@gkasprow Hope you're doing well. When you have a chance, could please you take a look at my changes?
https://github.com/sinara-hw/Fastino/issues/72#issuecomment-617446463
I think it is good enough. Every project can be done better, but here the main goal is high channel isolation. Let's produce it;
@gkasprow @cjbe @hartytp Could one of you please merge this?
I prefer to do it from my computer.
Did this get merged? Should we close now?
Did this get merged? Should we close now?
I believe @gkasprow didn't merge this, but re-comitted and pushed the final state to master.
@pathfinder49 my understanding is that all the work in this PR made its way into v1.1 so it's safe to close the PR. Please re-open if that's not the case.
I've addressed all issues with V1.0 I'm aware of. Specifically I've done addressed issues:
I still need to figure out how to mark the parallel termination capacitors as DNP. I'm also unsure if component clearances may pose a problem (design rules pass).
@gkasprow Could you please review my changes?