Closed hartytp closed 3 years ago
https://github.com/sinara-hw/Fastino/issues/77#issuecomment-686530657
I would not put time into that. The jitter in the FPGA, the ISI, crosstalk between the lines, and the PLL delay resolution are larger than the mismatch.
consensus is not to bother at least for this release
https://github.com/sinara-hw/Fastino/issues/77#issuecomment-686530657