Open airwoodix opened 5 years ago
As discussed in m-labs/migen#180, the pinout and schematics indicate the serial wire names from the µC perspective. Should at least the netlist be changed to reflect the FPGA perspective?
The decent solution is probably: The net should be called cpu_tx or fpga_rx and then the fpga platform can call it rx and the CPU code can call it tx.
Of course, cts and rts need to be crossed as well.
cts
rts
As discussed in m-labs/migen#180, the pinout and schematics indicate the serial wire names from the µC perspective. Should at least the netlist be changed to reflect the FPGA perspective?