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sinara-hw / KASLI-DIOT

DI/OT version of Kasli
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Keep slot signals in the same bank #11

Closed marmeladapk closed 1 month ago

marmeladapk commented 1 month ago

If that's not possible then keep clock capable signals with the same byte (so lvds0 and lvds1-7 in the same bank and lvds8 and lvds 9-15 in the same bank).

filipswit commented 1 month ago

Can you point which exactly are wrongly connected?

marmeladapk commented 1 month ago

On a closer look I didn't find any problems. I must have misread signal names in bank 2.