FPGA bank decoupling - Githubissues

sinara-hw / KASLI-DIOT

DI/OT version of Kasli

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Open marmeladapk opened 1 month ago

marmeladapk commented 1 month ago

P1V5 has decoupling only for 1 bank, not for 2
P2V5 is missing one set of decoupling capacitors (decoupling for 8 banks, not 9)

Otherwise MGT decoupling seems excessive given Xilinx' recommendations but is fine.