Open marmeladapk opened 1 month ago
Also DNP R12 in CMOS variant
Datasheet says that for LVCMOS source and sink vdd should be equal. We have P2V5 for source and P3V3 for sink. But we still clear the bar for V_ih in single ended mode.
Also DNP R12 in CMOS variant
Datasheet says that for LVCMOS source and sink vdd should be equal. We have P2V5 for source and P3V3 for sink. But we still clear the bar for V_ih in single ended mode.