compare with kasli 2.1 - Githubissues

sinara-hw / Kasli-SOC

Xilinx ZynQ(R) version of Kasli FPGA controller.

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Open hartytp opened 3 years ago

hartytp commented 3 years ago

Let's check that all relevant changes from Kasli >= 2.0 have been included in this

gkasprow commented 3 years ago

I recently added 6pins spaced by 2.54mm to support 4 direct IOs

filipswit commented 3 years ago

Ok, I can fit additional 4 IOs. I've noticed that SMA input is biased to 1.25V after balun instead of AC coupled.

gkasprow commented 3 years ago

I already added the IOs. The FPGA actually needs DC coupling. It supports native LVDS (2.5V) and internal termination.

filipswit commented 3 years ago

But last commit is mine and is without it.

gkasprow commented 3 years ago

I didn't do the commit yet so don't modify your project