SD_DET should be pulled up with 50k

sinara-hw / Kasli-SOC

Xilinx ZynQ(R) version of Kasli FPGA controller.

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Closed marmeladapk closed 3 years ago

marmeladapk commented 3 years ago

The CDn and WPn lines should both be pulled up with their own 50 kΩ resistors to the MIO I/O voltage.

UG933