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sinara-hw
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Kasli-SOC
Xilinx ZynQ(R) version of Kasli FPGA controller.
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Add additional filtering on P12V0 input to buck
#44
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marmeladapk
closed
3 years ago
marmeladapk
commented
3 years ago
https://github.com/sinara-hw/Kasli/issues/66
https://github.com/sinara-hw/Kasli/issues/66