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sinara-hw / Kasli-SOC

Xilinx ZynQ(R) version of Kasli FPGA controller.
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Ethernet PHY reset may need to be asserted during power up #53

Closed sbourdeauducq closed 2 years ago

sbourdeauducq commented 3 years ago

The Zynq cannot do it. Not sure if another reset after power-up is sufficient. Currently (without any reset) Ethernet communications work but not MDIO. image

sbourdeauducq commented 3 years ago

On the ZC706 (with a similar but not identical PHY) they have a gate to generate the power-up reset, so this could be important. image

sbourdeauducq commented 3 years ago

corresponding firmware issue: https://git.m-labs.hk/M-Labs/zynq-rs/issues/78

sbourdeauducq commented 3 years ago

Having or not having a power-up reset does not seem to make a difference, PHY works in both cases. Tested by @TopQuark12 I don't know if we should modify the board to comply with what the datasheet seems to say, and I'll leave that decision to @gkasprow

TopQuark12 commented 3 years ago

Current hardware configuration works fine as is, holding rst down during power on for > T_PU_RESET before de-asserting does not seem to affect the behavior of the phy chip during observation. Would be helpful if the schematics indicate the PHY MDIO address is 0.

gkasprow commented 2 years ago

added note