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Kasli-SOC
Xilinx ZynQ(R) version of Kasli FPGA controller.
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Changelog v1.1.1
#73
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maciejprzybysz
opened
1 year ago
maciejprzybysz
commented
1 year ago
Minor changes:
[x] TOP level schematic document had invalid version number (v1.0)
[x] Unnecessary "NO ERC" directive on Kasli-SOC_QUAD_BUCK.SchDoc X:50mil Y:6500mil
[x] J25 is moved away from the board edge in v1.1 - no change in v1.1.1, just noticed here (no issue nor changelog about that found)
[x] Validation errors/warnings corrected
[x] IC4 hidden GND pin
[x] synchronize ports and sheet entries on Kasli-SOC_top.SchDoc sheet symbols (harness types)
[x] DRC errors (no net via + poly top/bot)
[x] Changed version number on panel (was v1.0)
Minor changes: